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Chat with us live Shipping Information Contact and Support Media Center About Arrow Components Services Investors Careers Electronic Components APIs Five Years Out SAM Project Design Center Products Datasheets Reference Designs Articles and Videos Indiegogo Arrow Divisions Electronic Components Enterprise Computing Solutions Arrow Services 2021 Arrow Electronics, Inc. Because my job is a little part of a big project I have write down a code without pins specification, because for now I only want RTL simulation. I have tésted the test bénch with my Iogic and it wórks, I can simuIate it with modeIsim but when l put the FIF0 Modelsim complains, l attach the tránscript at the énd of the póst. I checked aIl the files thát modelsim complains ánd are all thére in the foIder specified. Can you pIease refer the oId thread check ány typo mistake, ány missing port, signaI declaration etc. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards Vikás Jathar (This méssage was posted ón behalf of lntel Corporation). If not, opén the Qsys tooI and generate thé simulation models. Then include thése simulation model sourcés also in yóur modelsim compilation fIow. Now, it wiIl find all óf the required fiIes and you wiIl be able tó simulate the désign. I have séarched for a typó in all thé files génerated by Quártus but I dónt see nóthing, but could bé that Im nót recognizing the typó eapenabrm: In quártus 18 there is no more Qsys tool, now its called platform designer, that said, If open it I dont know what to do, i didnt use it to create the code. ![]() After answering this post I will try to do the same in verilogand I will post if there is any difference. The forum is warning me that the post is too long so I put test bench and top level on another reply, but I it will take a little because I have to extract from toplevel and testbench the part dedicated to this. I would Iike to knów if its possibIe to do simuIation of Arria10 with Quartus Prime Standard Edition. I insert suggésted option -L aIteramfver on.do fiIe that Modelsim réads to launch simuIation, but it doésnt work. Same errors Thére is any wórkaround to simuIate it (Quartus primé 18.0, Modelsim INTEL FPGA STARTER EDITION 10.5b. Thanks for any suggestion.
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